The method of tracing the history of chip packaging and cutting a single unit from the entire wafer before subsequent packaging and testing has always been the "prescribed paradigm" for semiconductor chip manufacturing. However, with the rapid increase in chip manufacturing costs and the continuous pursuit of chip performance in the consumer market, people have begun to realize the necessity of innovating advanced packaging technology.

　　The reform and innovation of traditional packaging methods have led to the emergence of wafer level packaging (Wafer Level Package, WLP).

　　Wafer-level packaging technology can be defined as: most or all of the packaging and testing procedures are directly performed on the wafer, and then solder balls are installed and cut to produce individual IC finished units (as shown in the figure below).

　　Compared with wire-bond and flip-chip packaging technologies, wafer-level packaging technology can eliminate metal wiring, epitaxial pins (such as QFP), substrates or lead frames, etc. So it has the advantages of small package size and good electrical performance.

　　Leaders in the packaging industry mostly produce advanced wafer-level packaging products based on the wafer model. Not only can the existing wafer-level manufacturing equipment be used to complete the main packaging process, but also the packaging structure and chip layout design can be parallel Become a reality, thereby significantly shortening the design and production cycle and reducing the overall project cost.

　　The main advantages of advanced wafer level packaging include:

　　Shorten the design and production cycle and reduce the overall project cost;

　　Realize high-density I/O interconnection at the wafer level and reduce the line spacing;

　　Optimize electrical and thermal characteristics, especially suitable for applications such as radio frequency/microwave, high-speed signal transmission, and ultra-low power consumption;

　　The package size is smaller and the materials used are less, which is a perfect fit with the thin, short, and affordable smart phones and wearable products;

　　Realize multi-functional integration, such as System in Package (SiP), Integrated Passive Devices (IPD), etc.

　　需要强调的一点是，与打线型封装技术不同，用晶圆级封装技术来实现腔内信号布线(Internal Signal Routing)有多个选项：晶圆级凸块(Wafer Bumping)技术、再分布层(Re-Distribution Layer)技术、硅介层(Silicon Interposer)技术、硅穿孔(Through Silicon Via)技术等。

　　先进晶圆级封装技术，主要包括了五大要素：

　　圆级凸块(Wafer Bumping)技术;

　　扇入型(Fan-In)晶圆级封装技术;

　　扇出型(Fan-Out)晶圆级封装技术;

　　2.5D 晶圆级封装技术(包含IPD);

　　3D 晶圆级封装技术(包含IPD)。

　　作为芯片封装行业内的先锋，随着芯片尺寸和光刻节点缩小，长电科技正在全面推进晶圆级封装技术各细分领域的技术研发。在晶圆级凸块技术、扇入型晶圆级封装技术、扇出型晶圆级封装技术、2.5D 和 3D 晶圆级封装技术领域，长电科技都有着足够完善的集成解决方案。

　　晶圆凸块(Wafer Bumping)，顾名思义，即是在切割晶圆之前，于晶圆的预设位置上形成或安装焊球(亦称凸块)。晶圆凸块是实现芯片与 PCB 或基板(Substrate)互连的关键技术。凸块的选材、构造、尺寸设计，受多种因素影响，如封装大小、成本及电气、机械、散热等性能要求。

　　长电科技在晶圆凸点设计和工艺流程等方面具有丰富的经验，业务涵盖印刷型凸点(Printed Bump)技术、共晶电镀型落球(Ball Drop with Eutectic Plating)技术、无铅合金(Lead-Free Alloy)及铜支柱合金(Copper-Pillar Alloy)凸点技术等，并经量产验证适用于 8 英寸(200mm)和 12 英寸(300mm)大小的标准硅晶圆。

　　扇入型晶圆级封装(Fan-In Wafer Level Package，FIWLP)技术，业内亦称晶圆级芯片规模封装(Wafer Level Chip Scale Package，WLCSP)技术，是当今各类晶圆级封装技术中的主力。近两年，扇入型晶圆级封装产品的全球出货量都保持在每年三百亿颗以上，主要供给手机、智能穿戴等便携型电子产品市场。

　　随着便携型电子产品的空间不断缩小、工作频率日益升高及功能需求的多样化，芯片输入/输出(I/O)信号接口的数目大幅增加，凸块及焊球间距(Bump Pitch & Ball Pitch)的精密程度要求渐趋严格，再分布层(RDL)技术的量产良率也因此越发受重视。在这种背景下，扇出型封装(Fan-Out Wafer Level Package，FOWLP) 及扇入扇出混合型(Hybrid Fan-In/Fan-Out)等高端晶圆级封装技术应运而生。下图所示为FIWLP(左)、FOWLP(右)的典型结构：

    　在晶圆级封装制程里, 再分布层(Re Distribution Layer, RDL)技术主要用于在裸芯(Bare Die)和焊球之间重新规划(也可理解为优化)信号布线、传输的路径，以达到将晶圆级封装产品的信号互联密度、整体灵活度最大化的目的。RDL 的技术核心，简单来说就是在原本的晶圆上附加一层或多层的横向连接，用来传输信号。

　　下图所示为典型的 Chip-First RDL 方案。值得注意的是，在该方案中有两层电介质(Dielectric)材料，用来保护被其包裹的 RDL 层(可理解为应力缓冲)。另外，凸块冶金(Under Bump Metallurgy，UBM)技术在这里也派上了用场，来帮助触点(Contact Pad)支撑焊球、RDL 还有电介质。

　　With the popularization of ultra-high-density multi-chip modules (MCM) and even system-in-package (SiP) products in the fields of 5G, AI, high-performance computing, and automotive autonomous driving, 2.5D and 3D wafer-level packaging technologies Favored by designers. The figure below shows 2.5D (left) and 3D (right) wafer-level packaging technology.

　　As shown on the left of the figure above, for 2.5D wafer-level packaging technology, the signal interconnection of the two chips can be achieved through redistribution layer (Re-Distribution Layer, RDL) or silicon interposer (Silicon Interposer) technology.

　　As shown on the right of the figure above, for 3D wafer-level packaging technology, the signal interconnection of logic and communication chips such as CPU, GPU, ASIC, and PHY can also be through redistribution layer (RDL) or silicon interposer (Silicon Interposer). ) Technology to achieve. However, the signal interconnection between a plurality of high-bandwidth memory (High-Bandwidth Memory, HBM) chips stacked in 3D and a logic chip at the bottom is implemented by through silicon via (TSV) technology. Of course, how to choose between the above types of interconnects requires specific analysis based on actual specifications and cost targets.

　　Regardless of whether you focus on the present or the future, with the rush of major technology trends such as 5G, artificial intelligence, and the Internet of Things, wafer-level packaging technology will surely occupy a place in the technology competition of high-density heterogeneous integration.