Wafer testing is to test each die on the wafer, attach a probe made of gold wire to the inspection head to make a probe (probe) as thin as a hair, and contact the pad on the die to test its electrical Characteristics, unqualified dies will be marked, and then when the wafer is cut into separate dies based on the die, the unqualified dies marked with the mark will be eliminated and the next process will not be carried out to avoid Increased manufacturing costs.

　　After the wafer is manufactured, the wafer test is a very important test. This test is the transcript of the wafer production process. During the test, the electrical capabilities and circuit functions of each chip are detected. Wafer testing is also called die sorting or wafer sorting.

　　During the test, the wafer is fixed on a vacuum suction chuck and aligned with the thin probe electrical detector, while the probe is in contact with each bonding pad of the chip (Figure 4.18). The electrical tester tests the circuit under the drive of the power supply and records the results. The number, sequence and type of tests are controlled by computer programs. The testing machine is automated, so the test work after the probe electrical tester is aligned with the first wafer (manual alignment or using an automatic vision system) does not require the assistance of an operator.

　　The test is for the following three goals. First, before the wafer is sent to the packaging factory, qualified chips are identified. Second, the electrical parameters of the device/circuit are evaluated for characteristics. Engineers need to monitor the distribution of parameters to maintain the quality level of the process. Third, the accounting of qualified and defective chips will provide comprehensive performance feedback to wafer production personnel. The positions of qualified chips and defective products on the wafer are recorded on the computer in the form of a wafer map. The old technology in the past painted a dot of ink on the defective chip.

　　Wafer testing is one of the main statistical methods for chip yield. With the increase in chip area and density, the cost of wafer testing is increasing. As a result, the chip requires longer test time and more sophisticated power supplies, mechanical devices, and computer systems to perform test work and monitor test results. The visual inspection system also becomes more sophisticated and expensive as the chip size expands. Chip designers are required to introduce test patterns into the storage array. Test designers are exploring how to simplify the test process more efficiently and effectively. For example, the simplified test procedure can be used after the chip parameter evaluation is qualified. In addition, the chips on the wafer can be tested alternately, or the test of multiple chips can be performed at the same time.